The present invention relates to the field of printed circuit boards, and more particularly to a printed circuit board comprising an internal electrical component positioned within a via of the printed circuit board to suppress impedance and/or save space.
A printed circuit board is a board that may hold integrated circuits commonly referred to as chips and other electronic components. Typically, a printed circuit board is made of conductive layers separated by non-conductive dielectric. Conductive pathways commonly referred to as vias may interconnect electrical components on different layers of the board. The vias may be created by drilling through the printed circuit board at the appropriate place where two or more layers will interconnect and allowing conductive material, e.g., copper, to run through the hole. The conductive material, e.g., copper, may coat only the side of the hole or fill the entire hole.
When high frequency Alternating Current (AC) signals change layers in a printed circuit board, an undesirable electrical disturbance commonly referred to as electromagnetic interference is produced as illustrated in FIG. 1. FIG. 1 illustrates a prior art printed circuit board 100 comprising a plurality of conductive layers 110A-F separated by non-conductive dielectric. Printed circuit board 100 further comprises a plurality of vias 150A-C. Layers 110A-F may collectively or individually be referred to as layers 110 or layer 110, respectively. Vias 150A-C may collectively or individually be referred to as vias 150 or via 150, respectively. As stated above, electromagnetic interference may result when high frequency AC signals change layers in a printed circuit board. For example, an input signal, e.g., high frequency AC signal, may travel along a path commonly referred to as a transmission line from a source 120 to a load 130. The transmission line may be formed from two separate conductive paths. The first conductive path, commonly referred to as the signal path, may be from the etch, i.e., trace, on the top signal layer 110, i.e., layer 110A, of printed circuit board 100 to the etch, i.e., trace, on the bottom signal layer 110, i.e., layer 110F, through via 150A of printed circuit board 100. The second conductive path, commonly referred to as the reference path, may be between the reference layers 110 nearest to the conductive signal path, e.g., path between layers 110E and 110B. As the difference between the impedance of the input signal and reference layers 110, e.g., layers 110B, 110E, increases, energy may be lost. The lost energy may appear as undesirable noise commonly referred to as electromagnetic interference. When a high frequency AC signal changes layers 110 in printed circuit board 100, an impedance break may occur at the reference layer 110, e.g., layer 110B, nearest to the signal line, e.g., layer 110A. The impedance break may result in a large impedance difference increasing undesired electromagnetic interference.
In prior art printed circuit boards, electromagnetic interference may be reduced by placing a surface mount capacitor on the outside layer of the printed circuit board as illustrated in FIG. 1. A surface mount capacitor 140 may be mounted on the surface layer 110, e.g., layer 110A, of printed circuit board 100 to reduce the undesirable impedance of the reference path side of the transmission line. Typically, surface mount capacitor 140 may be placed near the bus or data path commonly referred to as the high frequency via 150, e.g., via 150A, where the input signal, i.e., source signal, travels from the top signal layer 110, i.e., layer 110A, to the bottom signal layer 110, i.e., layer 110F. By placing surface mount capacitor 140 near the high frequency via 150, i.e., via 150A, an AC low impedance path between reference layers 110B and 110E through surface mount capacitor 140 may be formed thereby reducing the electromagnetic interference generated.
As the frequency of the source signal increases the impedance of the vias 150, e.g., vias 150B-C, used to connect surface mount capacitor 140 between the reference layers 110, e.g., layers 110B, 110E, increases. As the impedance of the vias 150, e.g., vias 150B-C, increases, the impedance mismatch of the transmission line may be increased thereby creating electromagnetic interference. Subsequently, the frequency range of the input signal may be limited.
It would therefore be desirable to reduce the impedance within the reference path side of the high frequency transmission line. It would further be desirable to save space in the printed circuit board.
The problems outlined above may at least in part be solved in some embodiments by embedding an electrical component within a via of the printed circuit board to reduce the impedance within the reference path and/or saving space within the printed circuit board.
In one embodiment, a printed circuit board comprises a plurality of conductive layers where one of the plurality of conductive layers is a first layer, e.g., top signal layer, and one of the plurality of conductive layers is a second layer, e.g., bottom signal layer. The printed circuit board further comprises two or more vias for interconnecting two or more conductive layers. One of the two or more vias is part of a signal path configured to carry a source signal from the first layer to the second layer. Furthermore, one of the two or more vias is part of a reference path configured to carry the source signal from a third layer to a fourth layer. The printed circuit board further comprises an electrical component embedded in the via that is part of the reference path between two conductive layers to reduce the impedance within the reference path.
In another embodiment of the present invention, a printed circuit board comprises a plurality of conductive layers. The printed circuit board further comprises two or more vias for interconnecting two or more conductive layers. The printed circuit board further comprises an electrical component embedded in a particular via between two conductive layers instead of placing the electrical component on the surface of the printed circuit board thereby saving space within the printed circuit board.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.